1. Field of the Invention
The present invention generally relates to a method for fabricating a pixel structure, and more particularly, to a method for fabricating a pixel structure having a color filter layer through photo engraving processes (PEP).
2. Description of Related Art
Liquid crystal display (LCD) has replaced cathode ray tube (CRT) display as the mainstream in the display market because it has such advantages as high image quality, small volume, light weight, low driving voltage, low power consumption, and broad application, etc. A conventional LCD panel is composed of a color filter substrate having a color filter layer, a thin film transistor (TFT) array substrate, and a liquid crystal layer disposed between foregoing two substrates. In order to increase the resolution of the LCD panel and the aperture ratio of the pixels and to avoid alignment error between the color filter substrate and the TFT array substrate, a technique for integrating the color filter layer directly into the TFT array substrate (color filter on array, COA) is further provided.
FIGS. 1A˜1G are diagrams illustrating a conventional technique for forming a color filter layer on a TFT array substrate, wherein three pixel structures are illustrated as examples. First, referring to FIG. 1A, a substrate 10 is provided, and a gate 20 is formed on the substrate 10 through a first photo engraving process (PEP). Then, referring to FIG. 1B, a gate insulation layer 30 is formed on the substrate 10 to cover the gate 20, and a channel layer 40 and an ohmic contact layer 42 are formed on the gate insulation layer 30 above the gate 20 through a second PEP. Next, referring to FIG. 1C, a source 50 and a drain 60 are formed on part of the channel layer 40 and part of the gate insulation layer 30 through a third PEP. Generally speaking, the channel layer 40 is made of amorphous silicon (a-Si), and the ohmic contact layer 42 is made of N-type heavily-doped a-Si such that the contact resistance between the channel layer 40 and the source 50 and the contact resistance between the channel layer 40 and the drain 60 can be reduced. The ohmic contact layer 42 is formed by performing N-type ion doping on the surface of a-Si.
Referring to FIG. 1C again, the source 50 and the drain 60 are respectively extended from both sides of the channel layer 40 onto the gate insulation layer 30 and expose parts of the channel layer 40, wherein the gate 20, the channel layer 40, the source 50, and the drain 60 form a TFT TH. Then, referring to FIG. 1D, a dielectric layer 70 covering the TFT TH is formed, and a red color filter pattern 82 is formed above the TFT TH through a fourth PEP, wherein the red color filter pattern 82 has a contact opening H1 which is located above the drain 60 of the TFT TH corresponding to the red color filter pattern 82.
After that, referring to FIG. 1E, a green color filter pattern 84 is formed above part of the TFT TH through a fifth PEP, and a contact opening H2 is formed within the green color filter pattern 84, wherein the contact opening H2 is located above the drain 60 of the TFT TH corresponding to the green color filter pattern 84. Next, referring to FIG. 1F, a blue color filter pattern 86 is formed above the remaining TFT TH through a sixth PEP, and a contact opening H3 is formed within the blue color filter pattern 86, wherein the contact opening H3 is located above the drain 60 of the TFT TH corresponding to the blue color filter pattern 86. As shown in FIGS. 1D˜1F, the color filter layer 80 composed of the red color filter pattern 82, the green color filter pattern 84, and the blue color filter pattern 86 is fabricated through three PEPs.
Thereafter, referring to FIG. 1G, the dielectric layer 70 exposed by the contact openings H1, H2, and H3 is removed through an etching process. After that, a pixel electrode 90 is formed on the color filter layer 80 through a seventh PEP. As shown in FIG. 1G, the pixel electrodes 90 of the pixel structures are electrically connected to the corresponding drains 60 respectively through the contact openings H1, H2, and H3. By now, the process for directly integrating the color filter layer 80 into the TFT array substrate is completed.
As described above, the conventional method for fabricating a color filter layer on a TFT array substrate requires at least seven PEPs therefore is very complicated and requires very high fabricating cost. In addition, masks having different patterns are required for fabricating the pixel structure through foregoing at least seven PEPs, and accordingly, the fabricating cost of the pixel structure cannot be reduced due to the high cost of these masks.